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1 sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation single chip programmable serial transceiver seven (7) drivers and seven (7) receivers software-selectable industry standard protocols: ? rs-232 (v.28) ? eia-530 ? rs-449 ? rs-422a (v.11, x.27) ? rs-485 ? v.35 independant driver and receiver mode selection +5v single power supply operation surface mount packaging sp503 charge pump receiver decode driver decode receivers drivers description the sp503 is a highly integrated serial transceiver that allows software control of its interface modes. it offers hardware interface modes for rs-232 (v.28), rs-422a (v.11), rs-449, rs-485, v.35, and eia-530. the sp503 is fabricated using low?power bicmos process technology, and incorporates a exar patented (5,306,954) charge pump allowing +5v only operation. now available in lead free packaging rxd 1 rdec 0 2 rdec 1 3 rdec 2 4 rdec 3 5 tten 6 scten 7 v cc 8 tdec 3 9 tdec 2 10 tdec 1 11 tdec 0 12 dtr 13 txd 14 txc 15 rts 16 rl 17 nc 18 dcd 19 rxc 20 ri 21 st 22 sten 23 ll 24 v cc 25 c 1 + 26 v dd 27 c 2 + 28 gnd 29 c 1 ? 30 c 2 ? 31 v ss 32 v cc 33 gnd 34 rr(a) 35 rr(b) 36 rt(a) 37 rt(b) 38 ic(a) 39 ic(b) 40 60 gnd 59 sd(b) 58 tr(a) 57 gnd 56 tr(b) 55 v cc 54 rs(a) 53 gnd 52 rs(b) 51 ll(a) 50 gnd 49 ll(b) 48 v cc 47 rl(a) 46 gnd 45 rl(b) 44 st(b) 43 gnd 42 st(a) 41 v cc 80 cts 79 sct 78 dsr 77 sct(b) 76 sct(a) 75 gnd 74 v cc 73 v cc 72 gnd 71 rd(b) 70 rd(a) 69 dm(b) 68 dm(a) 67 cs(b) 66 cs(a) 65 tt(b) 64 gnd 63 tt(a) 62 v cc 61 sd(a) sp503 sp503 multiprotocol transceiver
sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation 2 electrical characteristics t min to t max @ vcc = +5v 5% unless otherwise noted. min. typ. max. units conditions logic inputs v il 0.8 volts v ih 2.0 volts logic outputs v ol 0.4 volts i out = -3.2ma v oh 2.4 volts i out = 1.0ma rs-485 driver ttl input levels v il 0.8 volts v ih 2.0 volts outputs high level output +6.0 volts low level output ?0.3 volts differential output 1.5 5.0 volts r l =54 ? , c l =50pf balance 0.2 volts |v t | - |v t | open circuit voltage 6.0 volts output current 28.0 ma r l =54 ? short circuit current 250 ma terminated in ?7v to +12v transition time 120 ns rise/fall time, 10%?90% maximum transmission rate 5 mbps r l =54 ? propagation delay t phl 200 ns r l =54 ? t plh 200 ns r l =54 ? rs-485 receiver ttl output levels v ol 0.4 volts v oh 2.4 volts input high threshold +0.2 +12.0 volts (a)-(b) low threshold ?7.0 ?0.2 volts (a)-(b) common mode range ?7.0 +12.0 volts high input current refer to graph low input current refer to graph receiver sensitivity 0.2 volts over ?7v to +12v common mode range input impedance 12 k ? maximum transmission rate 5 mbps propagation delay t phl 200 ns t plh 200 ns v.35 driver ttl input levels v il 0.8 volts v ih 2.0 volts outputs differential output 0.44 0.66 volts with termination network in figure 6; r l =100 ? output impedance 50 150 ? with termination network in figure 6. short circuit impedance 135 150 165 ? with termination network in figure 6. transition time 40 ns maximum transmission rate 5 mbps r l =100 ? propagation delay t phl 200 ns r l =100 ? t plh 200 ns r l =100 ?
3 sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation electrical characteristics t min to t max @ vcc = +5v 5% unless otherwise noted. min. typ. max. units conditions v.35 receiver ttl output levels v ol 0.4 volts v oh 2.4 volts input receiver sensitivity 0.2 volts input impedance 90 100 110 ? with termination network in figure 6. short circuit impedance 135 150 165 ? with termination network in figure 6. maximum transmission rate 5 mbps propagation delay t phl 200 ns t plh 200 ns rs-422 driver ttl input levels v il 0.8 volts v ih 2.0 volts outputs differential output 2.0 5.0 volts r l =100 ? open circuit voltage,v o 6.0 volts balance 0.4 volts |v t | ? |v t | offset +3.0 volts short circuit current 150 ma v out =0v power off current 100 a v cc = 0v, v out = 0.25v transition time 60 ns rise/fall time, 10%-90% maximum transmission rate 5 mbps r l =100 ? propagation delay t phl 200 ns r l =100 ? t plh 200 ns r l =100 ? rs-422 receiver ttl output levels v ol 0.4 volts v oh 2.4 volts input high threshold +0.2 +6.0 volts (a)-(b) low threshold ?6.0 ?0.2 volts (a)-(b) common mode range ?7.0 +7.0 volts high input current refer to graph low input current refer to graph receiver sensitivity 0.2 volts v cm =+7v to -7v input impedance 4 k ? v cm =+10v to -10v maximum transmission rate 5 mbps propagation delay t phl 200 ns t plh 200 ns rs-232 driver ttl input level v il 0.8 volts v ih 2.0 volts outputs high level output +5.0 +15 volts r l =3k ? , v in =0.8v, v cc = 5v low level output ?15.0 ?5.0 volts r l =3k ? , v in =2.0v, v cc = 5v open circuit voltage ?15 +15 volts short circuit current 100 ma v out =0v power off impedance 300 ? v cc = 0v, v out = 2.0v
sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation 4 electrical characteristics t min to t max @ vcc = +5v 5% unless otherwise noted. min. typ. max. units conditions slew rate 30 v/s r l =3k ? , c l =15pf transition time 1.56 s r l =3k ? , c l =2500pf maximum transmission rate 120 kbps r l =3k ? , c l =2500pf propagation delay t phl 28 sr l =3k ? t plh 28 sr l =3k ? rs-232 receiver ttl output levels v ol 0.4 volts v oh 2.4 volts input high threshold 1.7 2.4 volts low threshold 0.8 1.2 volts receiver open circuit bias +2.0 volts input impedance 3 5 7 k ? v in =+15v to -15v maximum transmission rate 120 kbps propagation delay t phl 1s t plh 1s rs-423 driver ttl input levels v il 0.8 volts v ih 2.0 volts output open circuit v oltage 4.0 10.0 volts high level output +3.6 +6.0 volts r l =550 ? low level output ?6.0 ?3.6 volts r l =550 ? short circuit current 150 ma v out =0v power off current 100 a v cc = 0v, v out = 0.25v transition time 0.8 2.4 s rise/fall time, 10-90% maximum transmission rate 120 kbps r l =550 ? propagation delay t phl 28 sr l =550 ? t plh 28 sr l =550 ? rs-423 receiver ttl output levels v ol 0.4 volts v oh 2.4 volts input high threshold +0.2 +7.0 volts low threshold ?7.0 ?0.2 volts high input current refer to graph low input current refer to graph receiver sensitivity 0.2 volts v cm = +7v to -7v input impedance 4 k ? v in = +10v to -10v maximum transmission rate 120 kbps propagation delay t phl 1s t plh 1s power requirements v cc 4.75 5.25 volts i cc 20 30 ma v cc =5v; no interface selected environmental and mechanical operating temperature range 0 +70 c storage temperature range ?65 +150 c esd rating 1 kv hbm
5 sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation v.35 47.0ma 48.8ma 47.3ma 54.5ma 104.2ma 100.9ma 100.9ma rs-232 35.4ma 37.8ma 35.2ma 43.6ma 54.1ma 57.1ma 55.9ma rs-422 25.8ma 31.4ma 25.8ma 27.5ma 140.2ma 135.9ma 145.2ma rs-485 33.4ma 37.91ma 33.51ma 34.81ma 200.3ma 194.8ma 203.3ma rs-449 37.8ma 40.3ma 41.1ma 42.9ma 142.3ma 138.8ma 147.4ma eia-530 45.2ma 48.1ma 44.4ma 50.3ma 148.9ma 145.7ma 147.3ma +1.0ma ?0.6ma +12v +6v ?3v ?7v 1 unit load maximum input current versus voltage rs-485 receiver +3.25ma ?3.25ma +10v +3v ?3v ?10v maximum input current versus voltage rs-422 receiver +3.25ma ?3.25ma +10v +3v ?3v ?10v maximum input current versus voltage rs-423 receiver receiver input graphs power matrix mode open input input to 5v input to gnd ac signal input to 5v input to gnd ac signal conditions to input with load with load with load with external termination resistor network; input @ 60khz, load is 3k ? & 2500pf for rs-232 and 100y for v.35 input @ 60khz load is 100 ? for rs-422 450 ? for rs-423 input @ 60khz load is 100 ? for rs-422 450 ? for rs-423 input @ 2.5mhz load is 54 ? . input @ 2.5mhz load is 100 ? . input @ 60khz load is 3k ? & 2500pf for rs-232. typical @ 25c and v cc = +5v unless otherwise noted. input is applied to one driver.
sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation 6 other ac characteristics (typical @ 25c and nominal supply voltages unless otherwise noted) parameter min. typ. max. un its conditions delay time from enable mode to tri?state mode single?ended mode (rs-232, rs-423) t pzl ; enable to output low 190 ns 3k ? pull?up to output t pzh ; enable to output high 130 ns 3k ? pull?down to output t plz ; disable from output low 270 ns 5v to input t phz ; disable from output high 400 ns gnd to input differential mode (rs-422, rs-485, v.35) t pzl ; enable to output low 100 ns 3k ? pull?up to output t pzh ; enable to output high 100 ns 3k ? pull?down to output t plz ; disable from output low 130 ns 5v to input t phz ; disable from output high 140 ns gnd to input notes: 1. measured from 2.5v of r in to 2.5v of r out . 2. measured from one?half of r in to 2.5v of r out . 3. measured from 1.5v of t in to one?half of t out . 4. measured from 2.5v of r o to 0v of a and b. pinout? rxd 1 rdec 0 2 rdec 1 3 rdec 2 4 rdec 3 5 tten 6 scten 7 v cc 8 tdec 3 9 tdec 2 10 tdec 1 11 tdec 0 12 dtr 13 txd 14 txc 15 rts 16 rl 17 nc 18 dcd 19 rxc 20 ri 21 st 22 sten 23 ll 24 v cc 25 c 1 + 26 v dd 27 c 2 + 28 gnd 29 c 1 ? 30 c 2 ? 31 v ss 32 v cc 33 gnd 34 rr(a) 35 rr(b) 36 rt(a) 37 rt(b) 38 ic(a) 39 ic(b) 40 60 gnd 59 sd(b) 58 tr(a) 57 gnd 56 tr(b) 55 v cc 54 rs(a) 53 gnd 52 rs(b) 51 ll(a) 50 gnd 49 ll(b) 48 v cc 47 rl(a) 46 gnd 45 rl(b) 44 st(b) 43 gnd 42 st(a) 41 v cc 80 cts 79 sct 78 dsr 77 sct(b) 76 sct(a) 75 gnd 74 v cc 73 v cc 72 gnd 71 rd(b) 70 rd(a) 69 dm(b) 68 dm(a) 67 cs(b) 66 cs(a) 65 tt(b) 64 gnd 63 tt(a) 62 v cc 61 sd(a) sp503 pin assignments? clock and data group pin 1 ? rxd ? receive data; ttl output, sourced from rd(a) and rd(b) inputs. pin 14 ? txd ? ttl input ; transmit data source for sd(a) and sd(b) outputs. pin 15 ? txc ? transmit clock; ttl input for tt driver outputs. pin 20 ? rxc ? receive clock; ttl output sourced from rt(a) and rt(b) inputs. pin 22 ? st ? send timing; ttl input; source for st(a) and st(b) outputs. pin 37 ? rt(a) ? receive timing; analog input, inverted; source for rxc. pin 38 ? rt(b) ? receive timing; analog input, non-inverted; source for rxc. pin 42 ? st(a) ? send timing; analog output, inverted; sourced from st. pin 44 ? st(b) ? send timing; analog output, non-inverted; sourced from st. pin 59 ? sd(b) ? analog out ? send data, non-inverted; sourced from txd. pin 61 ? sd(a) ? analog out ? send data, inverted; sourced from txd. pin 63 ? tt(a) ? analog out ? terminal timing, inverted; sourced from txc pin 65 ? tt(b) ? analog out ? terminal timing, non?inverted; sourced from txc. pin 70 ? rd(a) ? receive data, analog input; inverted; source for rxd.
7 sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation pin 71 ? rd(b) ? receive data; analog input; non-inverted; source for rxd. pin 76 ? sct(a) ? serial clock transmit; analog input, inverted; source for sct. pin 77 ? sct(b) ? serial clock transmit: analog input, non?inverted; source for sct pin 79 ? sct ? serial clock transmit; ttl output; sources from sct(a) and sct(b) inputs. control line group pin 13 ? dtr ? data terminal ready; ttl input; source for tr(a) and tr(b) outputs. pin 16 ? rts ? ready to send; ttl input; source for rs(a) and rs(b) outputs. pin 17 ? rl ? remote loopback; ttl input; source for rl(a) and rl(b) outputs. pin 19 ? dcd? data carrier detect; ttl output; sourced from rr(a) and rr(b) inputs. pin 21 ? ri ? ring in; ttl output; sourced from ic(a) and ic(b) inputs. pin 24 ? ll ? local loopback; ttl input; source for ll(a) and ll(b) outputs. pin 35 ? rr(a)? receiver ready; analog input, inverted; source for dcd. pin 36 ? rr(b)? receiver ready; analog input, non-inverted; source for dcd. pin 39 ? ic(a)? incoming call; analog input, inverted; source for ri. pin 40 ? ic(b)? incoming call; analog input, non-inverted; source for ri. pin 45 ? rl(b) ? remote loopback; analog output, non-inverted; sourced from rl. pin 47 ? rl(a) ? remote loopback; analog output inverted; sourced from rl. pin 49? ll(b) ? local loopback; analog output, non-inverted; sourced from ll. pin 51 ? ll(a) ? local loopback; analog output, inverted; sourced from ll. pin 52 ? rs(b) ? ready to send; analog output, non-inverted; sourced from rts. pin 54 ? rs(a) ? ready to send; analog output, inverted; sourced from rts. pin 56 ? tr(b) ? terminal ready; analog output, non-inverted; sourced from dtr. pin 58 ? tr(a) ? terminal ready; analog output, inverted; sourced from dtr. pin 66 ? cs(a)? clear to send; analog input, inverted; source for cts. pin 67 ? cs(b)? clear to send; analog input, non-inverted; source for cts. pin 68 ? dm(a)? data mode; analog input, inverted; source for dsr. pin 69 ? dm(b)? data mode; analog input, non-inverted; source for dsr pin 78 ? dsr? data set ready; ttl output; sourced from dm(a), dm(b) inputs. pin 80 ? cts? clear to send; ttl output; sourced from cs(a) and cs(b) inputs. control registers pins 2?5 ? rdec 0 ? rdec 3 ? receiver decode register; configures receiver modes; ttl inputs. pin 6 ? tten ? enables tt driver, active low; ttl input. pin 7 ? scten ? enables sct receiver; active high; ttl input. pins 12?9 ? tdec 0 ? tdec 3 ? transmitter decode register; configures transmitter modes; ttl inputs. pin 23 ? sten ? enables st driver; active low; ttl input. power supplies pins 8, 25, 33, 41, 48, 55, 62, 73, 74 ? v cc ? +5v input. pins 29, 34, 43, 46, 50, 53, 57, 60, 64, 72, 75 ? gnd ? ground. pin 27 ? v dd +10v charge pump capacitor ? connects from v dd to v cc . suggested capaci- tor size is 22f, 16v.
sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation 8 pin 32 ? v ss ?10v charge pump capacitor ? connects from ground to v ss . suggested ca- pacitor size is 22f, 16v. pins 26 and 30 ? c 1 + and c 1 ? ? charge pump capacitor ? connects from c 1 + to c 1 ? . sug- gested capacitor size is 22f, 16v. pins 28 and 31 ? c 2 + and c 2 ? ? charge pump capacitor ? connects from c 2 + to c 2 ? . sug- gested capacitor size is 22f, 16v. note: nc pins should be left floating; internal signals may be present. pared to older less?efficient designs. the charge pump still requires four external capacitors, but uses a four?phase voltage shifting technique to attain symmetrical 10v power supplies. figure 3(a) shows the waveform found on the positive side of capcitor c2, and figure 3(b) shows the negative side of capcitor c2. there is a free? running oscillator that controls the four phases of the voltage shifting. a description of each phase follows. phase 1 ? v ss charge storage ?during this phase of the clock cycle, the positive side of capacitors c 1 and c 2 are initially charged to +5v. c l + is then switched to ground and the charge on c 1 ? is transferred to c 2 ? . since c 2 + is connected to +5v, the voltage potential across capacitor c 2 is now 10v. phase 2 ? v ss transfer ? phase two of the clock con- nects the negative terminal of c 2 to the v ss storage capacitor and the positive terminal of c 2 to ground, and transfers the generated ?l0v to c 3 . simultaneously, the positive side of capaci- tor c 1 is switched to +5v and the negative side is connected to ground. phase 3 ? v dd charge storage ? the third phase of the clock is identical to the first phase ? the charge transferred in c 1 produces ?5v in the negative terminal of c 1 , which is applied to the negative side of capacitor c 2 . since c 2 + is at +5v, the voltage potential across c 2 is l0v. phase 4 ? v dd transfer ? the fourth phase of the clock connects the negative terminal of c 2 to ground and transfers the generated l0v across c 2 to c 4 , the v dd storage capacitor. again, features? the sp503 is a highly integrated serial trans- ceiver that allows software control of its inter- face modes. the sp503 offers hardware inter- face modes for rs-232 (v.28), rs-422a (v.11), rs-449, rs-485, v.35, and eia-530. the inter- face mode selection is done via an 8?bit switch; four (4) bits control the drivers and four (4) bits control the receivers. the sp503 is fabricated using low?power bicmos process technol- ogy, and incorporates an exar patented (5,306,954) charge pump allowing +5v only operation. each device is packaged in an 80?pin quad flatpack package. the sp503 is ideally suited for wide area net- work connectivity based on the interface modes offered and the driver and receiver configurations. the sp503 has seven (7) independent drivers and seven (7) independent receivers. the seventh driver of the sp503 allows it to support applications which require two separate clock outputs making it ideal for dce applications. theory of operation the sp503 is made up of four separate circuit blocks ? the charge pump, drivers, receivers, and decoder. each of these circuit blocks is described in more detail below. charge?pump the charge pump is an exar patented design (5,306,954) and uses a unique approach com- v cc = +5v ?5v ?5v +5v v ss storage capacitor v dd storage capacitor c 1 c 2 c 3 c 4 + + ++ ? ? ? ? figure 1. charge pump phase 1.
9 sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation figure 3. charge pump waveforms +10v gnd gnd ?10v c 2 + c 2 ? a) b) v cc = +5v ?10v v ss storage capacitor v dd storage capacitor c 1 c 2 c 3 c 4 + + ++ ? ? ? ? figure 2. charge pump phase 2. and rs-423 drivers. for the rs-232 driver, the current requirement will be 3.5ma per driver, and for the rs-423 driver, the worst case current drain will be 11ma per driver. the external power supplies should provide a power supply sequence of : +l0v, then +5v, followed by ?l0v . drivers the sp503 has seven (7) independent drivers, two of which have separate active?low tri?state controls. if a half-duplex channel is required, this can be achieved with external connections. control for the mode selection is done via a four?bit control word. the sp503 does not have a latch; the control word must be externally latched either high or low to write the appropri- ate code into the sp503 . the drivers are pre- arranged such that for each mode of operation the relative position and functionality of the drivers are set up to accommodate the selected interface mode. as the mode of the drivers is changed, the electrical characteristics will change to support the requirements of clock, data, and control line signal levels. table 1 shows a sum- mary of the electrical characteristics of the driv- ers in the different interface modes. unused driver inputs can be left floating; however, to ensure a desired state with no input signal, pull? up resistors to +5v or pull?down resistors to ground are suggested. since the driver inputs are both ttl or cmos compatible, any value resistor less than 100k ? will suffice. simultaneously with this, the positive side of capacitor c 1 is switched to +5v and the negative side is connected to ground, and the cycle be- gins again. since both v+ and v ? are separately generated from v cc in a no?load condition, v+ and v ? will be symmetrical. older charge pump approaches that generate v ? from v+ will show a decrease in the magnitude of v ? compared to v+ due to the inherent inefficiencies in the design. the clock rate for the charge pump typically operates at 15khz. the external capacitors must be 22f with a 16v breakdown rating. external power supplies for applications that do not require +5v only, external supplies can be applied at the v+ and v ? pins. the value of the external supply volt- ages must be no greater than l0v. the current drain for the 10v supplies is used for rs-232,
sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation 10 v cc = +5v ?5v +5v ?5v v ss storage capacitor v dd storage capacitor c 1 c 2 c 3 c 4 + + ++ ? ? ? ? figure 4. charge pump phase 3. v cc = +5v +10v v ss storage capacitor v dd storage capacitor c 1 c 2 c 3 c 4 + + ++ ? ? ? ? figure 5. charge pump phase 4. there are three basic types of driver circuits ? rs-232, rs-423, and rs-485. the rs-232 driv- ers output a minimum of 5v level single? ended signals (with 3k ? and 2500pf loading), and can operate up to 120kbps. the rs-232 drivers are used in rs-232 mode for all signals, and also in v.35 mode where they are used as the control line signals. the rs-423 drivers output a minimum of 3.6v level single?ended signals (with 450 ? loading) and can operate up to 120kbps. open circuit v ol and v oh measurements may exceed the 6v limitation of rs-423. the rs-423 drivers are used in rs-449 and eia-530 modes as rl and ll outputs. the third type of driver supports rs-485, which is a differential signal that can maintain 1.5v differential output levels with a worst case load of 54 ? . the signal levels and drive capability of the rs-485 drivers allow the drivers to also support rs-422 requirements of 2v differen- tial output levels with 100 ? loads. the rs-422 drivers are used in rs-449 and eia-530 modes as clock, data, and some control line signals. the rs-485?type drivers are also used in the v.35 mode. v.35 levels require 0.55v signals with a load of 100 ? . in order to meet the voltage requirements of v.35, external series resistors with source impedance termination resistors must be implemented to voltage divide the driver outputs from 0 to +5v to 0 to +0.55v. figure 6 shows the values of the resistor network and how to connect them. the termination network also achieves the 50 ? to 150 ? source imped- ance for v.35. for applications that require v.11 signals for clock and data instead of v.35 levels, omit the external termination networks. all of the differential drivers, rs-485, rs-422, and v.35 can operate up to 5mbps. table 1. sp503 drivers pin label mode: rs-232 v.35 rs-422 rs-485 rs-449 eia-530 tdec 3 ?tdec 0 0000 0010 1110 0100 0101 1100 1101 sd(a) tri?state rs-232 v.35? rs-422? rs-485? rs-422? rs-422? sd(b) tri?state tri?state v.35+ rs-422+ rs-485+ rs-422+ rs-422+ tr(a) tri?state rs-232 rs-232 rs-422? rs-485? rs-422? rs-422? tr(b) tri?state tri?state tri?state rs-422+ rs-485+ rs-422+ rs-422+ rs(a) tri?state rs-232 rs-232 rs-422? rs-485? rs-422? rs-422? rs(b) tri?state tri?state tri?state rs-422+ rs-485+ rs-422+ rs-422+ rl(a) tri?state rs-232 rs-232 rs-422? rs-485? rs-423 rs-423 rl(b) tri?state tri?state tri?state rs-422+ rs-485+ tri?state tri?state ll(a) tri?state rs-232 rs-232 rs-422? rs-485? rs-423 rs-423 ll(b) tri?state tri?state tri?state rs-422+ rs-485+ tri?state tri?state st(a) tri?state rs-232 v.35? rs-422? rs-485? rs-422? rs-422? st(b) tri?state tri?state v.35+ rs-422+ rs-485+ rs-422+ rs-422+ tt(a) tri?state rs-232 v.35? rs-422? rs-485? rs-422? rs-422? tt(b) tri?state tri?state v.35+ rs-422+ rs-485+ rs-422+ rs-422+
11 sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation sp503 + 22f, 16v 22f (v cc decoupling) +5v, 5% + 22f 16v 25 27 26 30 28 31 32 22f 16v + + 22f, 16v v cc v dd c 1 + c 1 ? c 2 + c 2 ? v ss gnd charge pump v.35 external driver output termination resistors all v cc connections can be tied together. charge pump capacitors must be placed as close to the package as possible. 107 ? -5v 232 ? 232 ? 107 ? -5v 232 ? 232 ? 120 ? 50 ? 50 ? 120 ? 50 ? 50 ? v.35 external receiver input termination resistors receiver decode driver decode ext. latch 1 1 1 0 1 1 1 0 v.35 mode control word note: an external voltage of -5v, 5% is needed for the driver output termination resistors. these v.35 termination resistors comply with all the parameters specified in ccitt recommendation v.35. for other termination configurations, please consult factory. in5819 200 ? 200 ? 200 ? 200 ? 107 ? -5v 232 ? 232 ? 200 ? 200 ? 120 ? 50 ? 50 ? + figure 6. typical operating circuit
sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation 12 there are three basic types of receivers ? rs-232, rs-423, and rs-485. the rs-232 receiver is a single?ended input with a threshold of 0.8v to 2.4v. the rs-232 receiver has an operating voltage range of 15v and can re- ceive signals up to 120kbps. rs-232 receivers are used in rs-232 mode for all signal types, and in v.35 mode for control line signals. the rs-423 receivers are also single?ended but have an input threshold as low as 200mv. the input impedance is guaranteed to be greater than 4k ? , with an operating voltage range of 7v. the rs-423 receivers can operate up to 120kbps. rs-423 receivers are used for the ic signal in rs-449 and eia-530 modes, as shown in table 2 . the third type of receiver supports rs-485, which is a differential interface mode. the rs-485 receiver has an input impedance of 15k ? and a differential threshold of 200mv. since the characteristics of an rs-422 receiver are actually subsets of rs-485, the receivers for rs-422 requirements are identical to the rs-485 receivers. rs-422 receivers are used in rs-449 and eia-530 for receiving clock, data, and some control line signals. the rs-485 receivers are also used for the v.35 mode. v.35 levels require the 0.55v signals with a load of 100 ? . in order to meet the v.35 input imped- ance of 100 ? , the external termination network pin label mode: rs-232 v.35 rs-422 rs-485 rs-449 eia-530 rdec 3 ?rdec 0 0000 0010 1110 0100 0101 1100 1101 rd(a) undefined rs-232 v.35? rs-422? rs-485? rs-422? rs-422? rd(b) undefined 15k ? to gnd v.35+ rs-422+ rs-485+ rs-422+ rs-422+ rt(a) undefined rs-232 v.35? rs-422? rs-485? rs-422? rs-422? rt(b) undefined 15k ? to gnd v.35+ rs-422+ rs-485+ rs-422+ rs-422+ cs(a) undefined rs-232 rs-232 rs-422? rs-485? rs-422? rs-422? cs(b) undefined 15k ? to gnd 15k ? to gnd rs-422+ rs-485+ rs-422+ rs-422+ dm(a) undefined rs-232 rs-232 rs-422? rs-485? rs-422? rs-422? dm(b) undefined 15k ? to gnd 15k ? to gnd rs-422+ rs-485+ rs-422+ rs-422+ rr(a) undefined rs-232 rs-232 rs-422? rs-485? rs-422? rs-422? rr(b) undefined 15k ? to gnd 15k ? to gnd rs-422+ rs-485+ rs-422+ rs-422+ ic(a) undefined rs-232 rs-232 rs-422? rs-485? rs-423 rs-423 ic(b) undefined 15k ? to gnd 15k ? to gnd rs-422+ rs-485+ 15k ? to gnd 15k ? to gnd sct(a) undefined rs-232 v.35? rs-422? rs-485? rs-422? rs-422? sct(b) undefined 15k ? to gnd v.35+ rs-422+ rs-485+ rs-422+ rs-422+ receivers the sp503 has seven (7) independent receivers which can be programmed for six (6) different interface modes. one of the seven (7) receivers (sct) has an active?high enable control, as shown in the mode diagrams. control for the mode selection is done via a 4? bit control word that is independent from the driver control word. the coding for the drivers and receivers is identical. therefore, if the modes for the drivers and receivers are supposed to be identical in the application, the control lines can be tied together. like the drivers, the receivers are pre-arranged for the specific requirements of the interface. as the operating mode of the receivers is changed, the electrical characteristics will change to sup- port the requirements of clock, data, and control line receivers. table 2 shows a summary of the electrical characteristics of the receivers in the different interface modes. unused receiver in- puts can be left floating without causing oscilla- tion. to ensure a desired state of the receiver output, a pull?up resistor of 100k ? to +5v should be connected to the inverting input for a logic low, or the non?inverting input for a logic high. for single-ended receivers, a pull?down resistor to ground of 5k ? is internally con- nected, which will ensure a logic high output. table 2. sp503 receivers
13 sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation of figure 6 must be applied. the threshold of the v.35 receiver is 200mv. the v.35 receiv- ers can operate up to 5mbps. all of the differen- tial receivers can receive data up to 5mbps. decoder the sp503 has the ability to change the inter- face mode of the drivers or receivers via an 8? bit switch. the decoder for the drivers and receivers is not latched; it is merely a combina- tional logic switch. the codes shown in tables 1 and 2 are the only specified, valid modes for the sp503 . undefined codes may represent other interface modes not specified or random out- puts (consult the factory for more information). the drivers are controlled with the data bits labeled tdec 3 ?tdec 0 . the drivers can be put into tri-state mode by writing 0000 to the driver decode switch. the receivers are controlled with data bits rdec 3 ?rdec 0 ; the code 0000 written to the receivers will place the outputs in an undetermined state. all receivers, with the exception of sct, do not have tri-state capabil- ity; the outputs will either be high or lowdepending upon the state of the receiver input.
sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation 14 figure 7. mode diagram ? rs-232 rd(a) 70 rxd 1 rt(a) 37 rxc 20 13 dtr 58 tr(a) cs(a) 66 cts 80 16 rts 54 rs(a) dm(a) 68 dsr 78 17 rl 47 rl(a) rr(a) 35 dcd 19 24 ll 51 ll(a) ic(a) 39 ri 21 22 st 42 st(a) 23 sten sct(a) 76 sct 79 15 txc 63 tt(a) 6 tten scten 7 0 0 1 0 0 0 1 0 sten st tten tt scten sct 1 disabled 1 disabled 1 enabled 0 enabled 0 enabled 0 disabled 14 txd 61 sd(a) receivers drivers mode: rs-232 driver receiver tdec 3 tdec 2 tdec 1 tdec 0 rdec 3 rdec 2 rdec 1 rdec 0
15 sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation figure 8. mode diagram ? v.35 rd(a) 70 rxd 1 rd(b) 71 mode: v.35 driver receiver tdec 3 tdec 2 tdec 1 tdec 0 rdec 3 rdec 2 rdec 1 rdec 0 rt(a) 37 rxc 20 rt(b) 38 13 dtr 58 tr(a) cs(a) 66 cts 80 16 rts 54 rs(a) dm(a) 68 dsr 78 17 rl 47 rl(a) rr(a) 35 dcd 19 24 ll 51 ll(a) ic(a) 39 ri 21 sct(a) 76 sct 79 scten 7 sct(b) 77 1 1 1 0 1 1 1 0 sten st tten tt scten sct 1 disabled 1 disabled 1 enabled 0 enabled 0 enabled 0 disabled 14 txd 61 sd(a) 59 sd(b) 22 st 42 st(a) 44 st(b) 23 sten 15 txc 63 tt(a) 65 tt(b) 6 tten receivers drivers
sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation 16 figure 9. mode diagram ? rs-422 rd(a) 70 rxd 1 rd(b) 71 rt(a) 37 rxc 20 rt(b) 38 cs(a) 66 cts 80 cs(b) 67 dm(a) 68 dsr 78 dm (b) 69 rr(a) 35 dcd 19 rr(b) 36 ic(a) 39 ri 21 ic(b) 40 sct(a) 76 sct 79 scten 7 sct(b) 77 0 1 0 0 0 1 0 0 sten st tten tt scten sct 1 disabled 1 disabled 1 enabled 0 enabled 0 enabled 0 disabled 14 txd 61 sd(a) 59 sd(b) 22 st 42 st(a) 44 st(b) 23 sten 15 txc 63 tt(a) 65 tt(b) 6 tten 13 dtr 58 tr(a) 56 tr(b) 16 rts 54 rs(a) 52 rs(b) 17 rl 47 rl(a) 45 rl(b) 24 ll 51 ll(a) 49 ll(b) receivers drivers mode: rs-422 driver receiver tdec 3 tdec 2 tdec 1 tdec 0 rdec 3 rdec 2 rdec 1 rdec 0
17 sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation figure 10. mode diagram ? rs-449 rd(a) 70 rxd 1 rd(b) 71 rt(a) 37 rxc 20 rt(b) 38 cs(a) 66 cts 80 cs(b) 67 dm(a) 68 dsr 78 dm (b) 69 rr(a) 35 dcd 19 rr(b) 36 ic(a) 39 ri 21 sct(a) 76 sct 79 scten 7 sct(b) 77 1 1 0 0 1 1 0 0 sten st tten tt scten sct 1 disabled 1 disabled 1 enabled 0 enabled 0 enabled 0 disabled 14 txd 61 sd(a) 59 sd(b) 22 st 42 st(a) 44 st(b) 23 sten 15 txc 63 tt(a) 65 tt(b) 6 tten 13 dtr 58 tr(a) 56 tr(b) 16 rts 54 rs(a) 52 rs(b) 17 rl 47 rl(a) 24 ll 51 ll(a) receivers drivers mode: rs-449 driver receiver tdec 3 tdec 2 tdec 1 tdec 0 rdec 3 rdec 2 rdec 1 rdec 0
sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation 18 figure 11. mode diagram ? rs-485 rd(a) 70 rxd 1 rd(b) 71 rt(a) 37 rxc 20 rt(b) 38 cs(a) 66 cts 80 cs(b) 67 dm(a) 68 dsr 78 dm (b) 69 rr(a) 35 dcd 19 rr(b) 36 ic(a) 39 ri 21 ic(b) 40 sct(a) 76 sct 79 scten 7 sct(b) 77 0 1 0 1 0 1 0 1 sten st tten tt scten sct 1 disabled 1 disabled 1 enabled 0 enabled 0 enabled 0 disabled 14 txd 61 sd(a) 59 sd(b) 22 st 42 st(a) 44 st(b) 23 sten 15 txc 63 tt(a) 65 tt(b) 6 tten 13 dtr 58 tr(a) 56 tr(b) 16 rts 54 rs(a) 52 rs(b) 17 rl 47 rl(a) 45 rl(b) 24 ll 51 ll(a) 49 ll(b) receivers drivers mode: rs-485 driver receiver tdec 3 tdec 2 tdec 1 tdec 0 rdec 3 rdec 2 rdec 1 rdec 0
19 sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation figure 12. mode diagram ? eia-530 rd(a) 70 rxd 1 rd(b) 71 rt(a) 37 rxc 20 rt(b) 38 cs(a) 66 cts 80 cs(b) 67 dm(a) 68 dsr 78 dm (b) 69 rr(a) 35 dcd 19 rr(b) 36 ic(a) 39 ri 21 sct(a) 76 sct 79 scten 7 sct(b) 77 1 1 0 1 1 1 0 1 sten st tten tt scten sct 1 disabled 1 disabled 1 enabled 0 enabled 0 enabled 0 disabled 14 txd 61 sd(a) 59 sd(b) 22 st 42 st(a) 44 st(b) 23 sten 15 txc 63 tt(a) 65 tt(b) 6 tten 13 dtr 58 tr(a) 56 tr(b) 16 rts 54 rs(a) 52 rs(b) 17 rl 47 rl(a) 24 ll 51 ll(a) receivers drivers mode: eia-530 driver receiver tdec 3 tdec 2 tdec 1 tdec 0 rdec 3 rdec 2 rdec 1 rdec 0
sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation 20 sp502/sp503 evaluation board the sp502/sp503 evaluation board (eb) is designed to offer as much flexibility to the user as possible. each board comes equipped with an 80-pin qfp zero-insertion force socket to allow for testing of multiple devices. the con- trol lines and inputs and outputs of the device can be controlled either manually or via a data bus under software control. there is a 50-pin connector to allow for easy connection to an existing system via a ribbon cable. there are also open areas on the pc board to add addi- tional circuitry to support application-specific requirements. manual control the sp502/sp503eb will support both the sp502 or sp503 multi-mode serial transceiv- ers. when used for the sp502, disregard all notation on the board that is in [brackets] . the sp502 has a half-duplex connection between the rxt receiver and the tt driver. due to this internal connection, the rxt receiver inputs can be accessed via the tt(a) and tt(b) pins. if the user needs separate receiver input test pins, jumpers jp1 and jp2 can be inserted to allow for separate receiver inputs located at sct(a) and sct(b). the corresponding ttl output for this receiver is labeled as sct. this test point is tied to pin 79 of the sp502 or sp503 . pin 7 of the evaluation board is connected to the dip switch, and is labeled as (scten). when used with the sp502 , this pin should be switched to a low state. when the evaluation board is used with the sp503 , pin 7 is a tri-state control pin for the sct receiver. the transceiver i/o lines are brought out to test pins arranged in the same configuration as shown elsewhere in this data sheet. a top layer silk-screen shows the drivers and receivers to allow direct correlation to the data sheet. the transmitter and receiver decode bits are tied together and are brought out to a dip switch for manual control of both the driver and receiver interface modes. since the coding for the driv- ers and receivers is identical, the bits have been tied together. the dip switch has 7 positions, four of which are reserved for the tdec/rdec control and the other three are used as tri-state control pins. the labels that are in [brackets] apply only to the sp503 . if a logic one is asserted, the corresponding red led will be lit. if a zero is asserted, the corresponding red led will not be lit. software control a 50-pin connector brings all the analog and digital i/o lines, v cc , and gnd to the edge of the card. this can be wired to the user?s existing design via a ribbon cable. the pinout for the connector is described in the following section. when the evaluation board is operated under software control, the dlp switch should be set up so that all bits are low (all leds off). this will tie 20k ? pulldown resistors from the inputs to ground and let the external system control the state of the control inputs. power and ground requirements the evaluation board layout has been optimized for performance by using basic analog circuit techniques, the four charge-pump capacitors must be 22f (16v) and be placed as close to the unit as possible; tantalum capacitors are sug- gested. the decoupling capacitor must be a minimum of 1f; depending upon the operating environment, 10f should be enough for worst case situations. the ground plane for the part must be solid, extending completely under the package. the power supplies for the device should be as accurate as possible; for rated performance 5% is necessary. the power sup- ply current will vary depending upon the se- lected mode, the amount of loading and the data rate. as a maximum, the user should reserve 200ma for i cc . the worst-case operating mode is rs-485 under full load of six (6) drivers supplying 1.6v to 54 ? loads. the power and ground inputs can be supplied through either the banana jacks on the evaluation board (red = v cc = +5v5%; black = gnd) or through the con- nector. for reference, the 80-pin qfp socket is a tesco part number fpq-80-65-09a. the 50-pin connector is an amp part number 749075-5.
21 sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation figure 13. sp502/503 evaluation board schematic
sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation 22 figure 14a. evaluation board ? top layers
23 sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation figure 14b. evaluation board ? bottom layers
sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation 24 figure 15. external transient suppressors
25 sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation edge dut pin connector descriptions 01 txd (pin 14) ?ttl input ? transmit data; source for sd(a) and sd(b) out- puts. 02 dtr (pin 13) ? ttl input ? data terminal ready: source for tr(a) and tr(b) outputs. 03 st/tt (pin 6) ?ttl input ? st/tt select pin; enables st drivers and dis- ables tt drivers when high. disables st drivers and enables tt drivers when low. 04 dec 3 /rdec 3 (pin 5) ? ttl input ? transmitter/receiver decode register. 05 tdec 2 /rdec 2 (pin 4) ? ttl input ? transmitter/receiver decode register. 06 tdec 1 /rdec 1 (pin 3) ? ttl input ? transmitter/receiver decode register. 07 tdec 0 /rdec 0 (pin 2) ? ttl input ? transmitter/receiver decode register. 08 rxd (pin 1 ) ? ttl output ? receive data; sourced from rd(a) and rd)b) inputs. 09 cts (pin 80) ? ttl output ? clear to send; sourced from cs(a) and cs(b) inputs. 10 rxt (pin 79) ? ttl output ? rxt; sourced from tt(a), tt(b) inputs. 11 dsr (pin 78) ? ttl output ? data set ready; sourced from dm(a) and dm(b) inputs. 12 rd(b) (pin 71) ? analog in ? receive data, non?inverted; source for rxd. edge dut pin connector descriptions 13 rd(a) (pin 70) ? analog in ? receive data, inverted: source for rxd. 14 dm(b) (pin 69) ? analog in ? data mode, non?inverted; source for dsr. l5 dm(a) (pin 68) ? analog in ? data mode, inverted; source for dsr. 16 cs(b) (pin 67) ? analog in ? clear to send; non?inverted; source for cts. 17 cs(a) (pin 66) ? analog in ? clear to send, inverted; source for cts. 18 tt(b) (pin 65) ? analog out ? terminal timing, non?inverted: sourced from txc input. 19 tt(a) (pin 63) ? analog out ? terminal timing; inverted: sourced from txc input. 20 tr(a) (pin 58) ? analog out ? termi- nal ready, inverted; sourced from dtr. 21 tr(b) (pin 56) ? analog out ? termi- nal ready; non?inverted; sourced from dtr. 22 sd(a) (pin 61) ? analog out ? send data, inverted; sourced from txd. 23 sd(b) (pin 59) ? analog out ? send data; non?inverted; sourced from txd. 24 rs(a) (pin 54) ? analog out ? ready to send; inverted; sourced from rts. 25 rs(b) (pin 52) ? analog out ? ready to send, non?inverted; sourced from rts. 1 26 2 27 3 28 4 29 5 30 6 31 7 32 8 33 9 34 10 35 11 36 12 37 13 38 14 39 15 40 16 41 17 42 18 43 19 44 20 45 21 46 22 47 23 48 24 49 25 50
sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation 26 edge dut pin connector descriptions 26 st (pin 22) ? ttl input ? send tim- ing; source for st(a) and st(b) out- puts. sp503 only. 27 sten (pin 23) ? ttl input ? driver enable control pin; active low. sp503 only, 28 sct(a) (pin 76) ? analog input ? in- verting; input for sct receiver; sp503 only. 29 sct(b) (pin 77) ? analog input ? non? inverting; input for sct receiver. sp503 only. 30 v cc ? +5v for all circuitry. 31 gnd ? signal and power ground. 32 ll(a) (pin 51) ? analog out ? local loopback, inverted; sourced from ll. 33 ll(b) (pin 49) ? analog out ? local loopback, non?inverted sourced from ll. 34 rl(a) (pin 47) ? analog out ? remote loopback; inverted; sourced from rl. 35 rl(b) (pin 45) ? analog out ? remote loopback; non?inverted; sourced from rl. 36 st(b) (pin 44) ? analog out ? send timing, non?inverted; sourced from txc. 37 st(a) (pin 42) ? analog output ?send timing, inverted; sourced from txc. 38 ic(b) (pin 40) ? analog in ? incoming call; non?inverted; source for rl. edge dut pin connector descriptions 39 ic(a) (pin 39) ? analog in ? incoming call; inverted; source for rl. 40 rt(b) (pin 38) ? analog in ? receive timing, non?inverted; source for rxc. 41 rt(a) (pin 37) ? analog in ? receive timing; inverted; source from rxc. 42 rr(b) (pin 36) ? analog in ? receiver ready; non?inverted; source for dcd. 43 rr(a) (pin 35) ? analog in ? receiver ready; inverted; source for dcd. 44 ll (pin 24) ? ttl input ? local loopback; source for ll(a) and ll(b) outputs. 45 rl (pin 21) ? ttl output ? ring indicator; sourced from ic(a) and ic(b) inputs. 46 rxc (pin 20) ? ttl output ? receive clock; sourced from rt(a) and rt(b) inputs. 47 dcd (pin 19) ? ttl output ? data carrier detect; sourced from rr(a) and rr(b) inputs. 48 rl (pin 17) ? analog out ? remote loopback; source for rl(a) and rl(b) outputs. 49 rts (pin 16) ? ttl input ? ready to send; source for rs(a) and rs(b) out- puts. 50 txc (pin 15) ? ttl input ? transmit clock; source for tt(a) and tt(b) outputs. 1 26 2 27 3 28 4 29 5 30 6 31 7 32 8 33 9 34 10 35 11 36 12 37 13 38 14 39 15 40 16 41 17 42 18 43 19 44 20 45 21 46 22 47 23 48 24 49 25 50
27 sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation
sp503_101_101508 sp503 multiprotocol transceiver ? copyright 2008 exar corporation 28 ordering information part number top mark temperature range package types sp503cm-l ........ sp503cmyyww......0c to +70c ............................. 80?pin jedec (ms-022 bc) lqfp sp503em -l.........sp503emyyww......-20c to +85c ........................ 80?pin jedec (ms-022 bc) lqfp date revision description 1/27/04 a implemented tracking revision. 5/6/04 b added top mark to ordering information. 7/29/04 c included lqfp package option. 6/8/05 d note that the sp503 evaluation board is no longer available. the information is still included as reference material should customers desire to breadboard their own evaluation setup. 7/17/08 1.0.0 sp503 is no longer available in mqfp package per pcn 07-1102- 06a. in addition, sp503 is now only available in pb-free, rohs compliant packages. new package drawing has been included and ordering information has been updated. changed to exar datasheet format and revision to 1.0.0. 10/15/08 1.0.1 SP503EM-L temperature range changed from "-40c to +85c" to "-20c to +85c". added esd rating of 1kv hbm to electrical characteristics. revision history notice exar corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. exar corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. charts and schedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless exar corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2008 exar corporation datasheet september 2008 send your technical inquiry with details to: uarttechsupport@exar.com reproduction, in part or whole, without the prior written consent of exar corporation is prohibited.

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